`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module: ClockDivider                                                         //
// Author: Zhiyuan Lin                                                          //
// Date: 4/28/2014                                                              //
//////////////////////////////////////////////////////////////////////////////////
module ClockDivider(clk, o_clk, Pause);
    input clk, Pause;
    //input [3:0] difficulty;
    output reg o_clk;
    reg [23:0] count_4Hz; //4Hz refers to speed1, 8Hz refers to speed2

always @ (posedge clk) 
  begin
  if (Pause == 1) begin
  ;
  end
  else begin
  	 if(count_4Hz == 277778) // 138889 34722
	    begin
	      count_4Hz = 0;
	      o_clk= ~o_clk; // we get first speed
	    end
	    else begin
	      count_4Hz = count_4Hz +24'b1;
	    end
  end
 end
  
  
/*    case(difficulty)
	 0: if(count_4Hz == 138889) // 138889 34722
	    begin
	      count_4Hz = 0;
	      o_clk= ~o_clk; // we get first speed
	    end
	    else begin
	      count_4Hz = count_4Hz +24'b1;
	    end
		 
	1:  if(count_4Hz == 69444) // 69444 17361
	    begin
	    count_4Hz = 0;
	    o_clk= ~o_clk; // we get second speed
	    end
	    else begin
	    count_4Hz = count_4Hz +24'b1;
	    end
		 
	default:;
	endcase
end*/

	
endmodule
